VDMOS Enhanced MOS1 Model

VDMOS MOS1 Model

SuperSpice has an enhanced version of the standard MOS1 Shichman-Hodges model. The essential feature of the model has become referred to as the "VDMOS" model, first implemented by Linear Technology in their LTSpice product. The principal feature of this model is the implementation of nonlinear Gate Drain capacitance. However, it may be noted that this name is somewhat misleading in that this nonlinear nature is not something inherent to "Vertically diffused" or "Extended drain" type mosfets, but is an essential character of any and all mosfets. Specifically, low voltage, standard symmetrical lateral mosfets can exhibit a large increase in gate drain capacitance as the drain voltage falls below its gate voltage. This characteristic is fully understood and has been an inbuilt feature of BSim models ever since BSim were introduced. However, the issue with such models for many users, is that they are very complex and are generally only available to integrated circuit design companies that have signed a NDA. The problem solved by the "VDMOS" model is that model parameters may be chosen with comparative ease from data sheet graphs and tables.

SuperSpice has simplified the construction of a VDMOS models, by recognizing that apart from additional static capacitances, mosfets are, essentially, symmetrical with respect to source and drain, such that the core nonlinear capacitances may be specified by only three generally provided data sheet parameters. As such, SuperSpice allows direct model parameter input of:

CISS, COSS and CRSS

To set all essential capacitor parameters, apart from the voltage rate at which these capacitances transition from min to max values.

The SuperSpice enhanced VDMOS-MOS1 model provides the following extensions:

1 Nonlinear, CGD, CGS and CGB capacitances

2 Quasi-saturation (premature current limiting) at lower VDS

3 Subthreshold modeling with independent setting of the subthreshold exponential "io" value

4 Voltage breakdown, or increase of lambda at high vds

5 Gate resistance

Device Capacitances - Data Sheet Implementation

CGD and CGS use the same nonlinear parameters. Corrections may be made to this by specifying the existing MOS1 cgso and cgdo static capacitances. CGB may use an alternative set of parameters and functions, but defaults to the same set as CGD/CGS if not specified. Total input capacitance is a function of gate source and gate bulk nonlinear capacitance, however, the characteristics of the voltage dependency of CGS and CGB are such that the sum is almost constant, such that the data sheet specification of ciss is enough to set the model, without any capacitance being counted twice. The SuperSpice default model using ciss, crss and coss allow for accurate modeling over a full range of negative and positive gate source voltages, showing the correct fall of capacitance from negative voltages to a rise and mid range plateau to the final CGD increases when the device hits linear region operation as typically of full Bsim3 models. There are additional parameters, cgsdvth (CGD/CGS) and cgbvth (CGB) which sets transition voltages to account for gate capacitance not immediately starting to increase when vgs > 0. Typically it is of the order of vth0/2.

CRSS data sheet value sets model parameter CGD. This parameter sets the reverse feedback capacitance. Specify "crss" or "cgdmin" from the data sheet value of "crss"

CISS data sheet value sets model parameter CGS. This parameter sets the gate capacitance by subtracting CRSS. Specify "ciss" or "cgdmax" from the data sheet value of "ciss"

COSS data sheet value sets internal model parameter CBD. This parameter sets the drain body diode capacitance by subtracting CRSS. Specify "coss"

The main capacitance equations are:

for vgd < cgsdbvth

CGD = cgdc1* atan(cgda * (vgd - cgsdbvth)) + cgdco;

and

for vgd > cgsdbvth

CGD =cgdc1 * tanh(cgda * (vgd - cgsdbvth)) + cgdco

...and we refer you to LTSpice if you would like more details...excepting for the needed offset, which said simulator omits...

Typical Capacitance Plots

The test circuit for this graph used a 1V/S input ramp so that time=vgs. vgs is ramped from -5V to 10V, with vds=5V.

Green = CGB, Orange=CISS, Brown=CGS, Violet=CGD

Note: For this example model, if CGD were to be set very low, the orange (CISS) and green (CGB) would tend to overlay at negative vgs, as is more typical for a low voltage ic mosfets.

Note: SuperSpice allows for the direct plotting of cgs, cgd, cgd and ciss from its docked signal list of the waveform tab by ctrl-clicking on the signals mn1[cgd], mn1[cgs] and mn1[cgb], where mn1 is the particular name of the device inspected, noting that the "op" button needs to be active.

Subthreshold Current

SuperSpice implements modified Shichman-Hodges equations that allows for a fairly accurate approximation to real subthreshold conduction. It does this by translating Vgst, the gate overdrive voltage (vgs - vth0), by the following.

For vgst >> 0 v'gst -> (vgst - vsubthres)

Which results in, essentially, the same behaviour as the Shichman-Hodges model if vsubthres is small say, < 200mv

For vgst << 0

Which results in, nominal subthreshold behaviour, with independent control of io by vsubthres. A 200mv vsubthres may result in a 100 fold reduction in subthreshold current.

Quasi-Saturation

SuperSpice implements the Vincenzo d'Alessandro (2001) Quasi-Saturation Model. d'Alessandro has shown that accurate modeling of the quasi-saturation may be achieved by the addition of a nonlinear drain resistance, given by the following equation:

Typically, the last power term may be ignored, but is supported. SuperSpice uses the standard MOS1 "rd" parameter as the d'Alessandro R0 parameter. Other model parameters are "rq", "vq", "vsatq" and "nq",

Breakdown Voltage

SuperSpice implements an exponential breakdown current multiplier of:

This may be used to have an aggressive breakdown, or a more slower increase in output at high vds

Example Model

.MODEL ECF20N20_XN NMOS(level=1 vdmos=1 Vto=250m Kp=1.2 Lambda=5m Rs=10m Rd=400m ksubthres=50m
+ vsubthres=25m rq=100m vq=15 nq=25m vsatq=10 ciss=950p crss=20p coss=550p
+ cgda=2 cgba=2 cgdsvth=500m cgbvth=1 cgdsbmode=2 bv=210 nbv=30 ibv=10n
+ cgsdbtc=1m bv=200 ibv=1m nbv=100 rg=50)

SuperSpice MOS1-VDMOS Parameter Feature Table

The following summary table describes the parameters that have been added/modified from the standard MOS1 model, described in the Spice3 help

Parameter | Description | Typical value | Default value
"vdmos" | Selects VDMOS mode L=W=1 | 1 | 0
"ciss" | Data sheet setting of input capacitances. overrides cgdmax, cgdmin | 1n | 0
"crss" | Data sheet setting of input capacitances. overrides cgdmax, cgdmin and cbd | 50p | 0
"coss" | Data sheet setting of output capacitances. overrides cbd | 500p | 0
"cgdsa" | Capacitance transition rate for CGD/CGS | 5 | 1
"cgba" | Capacitance transition rate for CGB | 2 | 1
"crssvo" | Voltage at which crss is specified | 10 | 10
"cgdsbmode" | cap gate-drain-source-bulk modes Recommended mode is 2 0 LT Compatibility CGD only 1 Symetrical nonlinear CGD and CGS 2 CGB uses atan() for vgs > cgsdbvth, tanh() for vgs < cgsdbvth 3 CGB uses atan() for all vgs 4 CGB uses tanh() for all vgs | 1 | 1 LTSpice Compatibility
"cgdsvth" | Sets the zero point voltage for the capacitance cgs/cgd equations. Replaces vgs by vgs-cgdsvth. Typically capacitance does not start to increase at vgs=0 | vth0/2 | 0
"cgbvth" | Sets the zero point voltage for the capacitance cgb equations. Replaces vgs by vgs-cgbvth. Typically offset from cgdsvth |  | 0
"cgbmax" | Independent setting of cgbmax. Typically not necessary. | 1n | 0
"cgbmin" | Independent setting of cgbmin. Typically not necessary. | 50p | 0
"cgba" | Independent setting of transition rate rate. Typically lower than cgda and may be necessary for accurate modeling | 1 | 1
"capstc" | Temp co for all nonlinear capacitors | 1m | 0
"ksubthres" | Main exponent parameter setting subthreshold behaviour | 0.05 | 0
"vsubthres" | Offset to VGS sub-threshold transformation. Allows the basic io of the exponential region behaviour to be set, essentially, independently from large vgs region behavior. |  | 0
"nsubthres" | Alternative to setting vsubthres. Internal Vt (KT/q) is multiplied by nsubthres and used instead of ksubthres. | 2 | 1
"rg" | Gate resistance. Addition to MOS1 Required for accurate rise/fall/delay times | 50 | 0
"rd" | Existing MOS1 param used as quasi-sat ro |  | 0 (must be set not equal to zero if used)
"rq" | Main quasi-sat resistance parameter | 1 | 0
"vqs" | quasi-sat saturation voltage parameter | 100 |
"nq" | quasi-sat n (power) parameter | 0.025 | 0
"vsatq" | quasi-sat vsat parameter | 5 | 0 (must be set not equal to zero if used)
"bv" | Breakdown voltage param | 100 | 0 (means infinite or no breakdown)
"ibv" | Current ratio of increase in current at breakdown voltage | 1m | 100p (if bv not equal to 0)
"nbv" | Breakdown voltage exponential scale factor | 1 | 1
"trd1" | Temp Co 1 rd | 1m | 0
"trd2" | Temp Co 2 rd | 1u | 0
"trs1" | Temp Co 1 rs | 1m | 0
"trs2" | Temp Co 2 rs | 1u | 0
"trg1" | Temp Co 1 rg | 1m | 0
"trg2" | Temp Co 2 rg | 1u | 0
"tksubthres1" | Temp Co 1 ksubthres | 1m | 0
"tksubthres2" | Temp Co 2 ksubthres | 1u | 0
"tvsubthres1" | Temp Co 1 vsubthres | 1m | 0
"tvsubthres2" | Temp Co 2 vsubthres | 1u | 0
"tkp1" | Temp Co 1 kp | 1m | 0
"tkp2" | Temp Co 2 kp | 1u | 0
"tvto1"and "tvt01" | Temp Co 1 vto | 1m | 0
"tvto2"and "tvt02" | Temp Co 2 vto | 1m | 0
"tlambda1" | Temp Co 1 lambda | 1m | 0
"tlambda2" | Temp Co 2 lambda | 1u | 0
"cgdmax" | Maximum value of cgd, essentially equal to data sheet ciss value. Preferred param name is "ciss". Sets drain, gate and bulk capacitances. LTSpice compatible. | 1n | 0
"cgdmin" | Minimum value of cgd, essentially equal to data sheet crss value. Preferred param name is "crss". Sets drain, gate and bulk capacitances. LTSpice compatible. | 50p | 0
"a" | Gate voltage rate at which cmin goes to cmax. Preferred param name is "cgda". LTSpice compatible. | 5 | 1

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