Digital State Machine

The digital state machine provides for straightforward descriptions of clocked combinational logic blocks with a variable number of inputs and outputs and with an unlimited number of possible states. The model can be configured to behave as virtually any type of counter or clocked combinational logic block and can be used to replace very large digital circuit schematics with an identically functional but faster representation. The d state model is configured through the use of a state definition file (state.in) which resides in a directory of your choosing. The file defines all states to be understood by the model, plus input bit combinations which trigger changes in state. An example state.in file is shown below:

begin file
* This is an example state.in file. This file
* defines a simple 2bit counter with one input. The
* value of this input determines whether the counter counts
* up (in = 1) or down (in = 0).
0 0s 0s 0 -> 3
1 > 1
1 0s 1z 0 > 0
1 > 2
2 1z 0s 0 > 1
1 > 3
3 1z 1z 0 > 2
3 1z 1z 1 > 0
end file

Several attributes of the above file structure should be noted. First, ALL LINES IN THE FILE MUST BE ONE OF FOUR TYPES.

These are:

1. A comment, beginning with a ``*'' in the first column.

2. A header line, which is a complete description of the current state, the outputs corresponding to that state, an input value, and the state that the model will assume should that input be encountered. The first line of a state definition must ALWAYS be a header line.

3. A continuation line, which is a partial description of a state, consisting of an input value and the state that the model will assume should that input be encountered. Note that continuation lines may only be used after the initial header line definition for a state.

4. A line containing nothing but whitespace (space, formfeed, newline, carriage return, tab, vertical tab). A line which is not one of the above will cause a file loading error. Note that in the example shown, whitespace (any combination of blanks, tabs, commas) is used to separate values, and that the character ``>'' is used to underline the state transition implied by the input preceding it. This particular character is not critical in of itself, and can be replaced with any other character or nonbroken combination of characters that is required (e.g. ``==>'', ``>>'', ``:'', ``resolves to'', etc.) The order of the output and input bits in the file is important; the first column is always interpreted to refer to the ''zeroth'' bit of input and output. Thus, in the file above, the output from state 1 sets out[0] to ``0s'', and out[1] to ``1z''. The state numbers need not be in any particular order, but a state definition (which consists of the sum total of all lines which define the state, its outputs, and all methods by which a state can be exited) must be made on contiguous line numbers; a state definition cannot be broken into subblocks and distributed randomly throughout the file. On the other hand, the state definition can be broken up by as many comment lines as desired. Header files may be used throughout the state.in file, and continuation lines can be discarded completely,: continuation lines are primarily provided as a convenience.

Example SPICE Usage:

a4 [2 3 4 5] 1 12 [22 23 24 25 26 27 28 29] state_machine1
.model state_machine1 d_state(clk_delay = 13.0e9 reset_delay = 27.0e9 state_file = newstate.txt reset_state = 2)

NAME_TABLE:
C_Function_Name: cm_d_state
Spice_Model_Name: d_state
Description: ''digital state machine''
PORT_TABLE:
Port Name: in clk
Description: ''input'' ''clock''
Direction: in in
Default_Type: d d
Allowed_Types: [d] [d]
Vector: yes no
Vector_Bounds: [1 ]
Null_Allowed: yes no
PORT_TABLE:
Port Name: reset out
Description: ''reset'' ''output''
Direction: in out
Default_Type: d d
Allowed_Types: [d] [d]
Vector: no yes
Vector_Bounds: [1 ]
Null_Allowed: yes no
PARAMETER_TABLE:
Parameter_Name: clk_delay reset_delay
Description: ''delay from CLK'' ''delay from RESET''
Data_Type: real real
Default_Value: 1.0e9 1.0e9
Limits: [1.0e12 ] [1.0e12 ]
Vector: no no
Vector_Bounds:
Null_Allowed: yes yes
PARAMETER_TABLE:
Parameter_Name: state_file
Description: ''state transition specification file name''
Data_Type:

Execution Procedures
Predefined Code Models
XSPICE Simulator
Software User's Manual
Default_Value: ''state.txt''
Limits:
Vector: no
Vector_Bounds:
Null_Allowed: no
PARAMETER_TABLE:
Parameter_Name: reset_state
Description: ''default state on RESET & at DC''
Data_Type: int
Default_Value: 0
Limits:
Vector: no
Vector_Bounds:
Null_Allowed: no
PARAMETER_TABLE:
Parameter_Name: input_load
Description: ''input loading capacitance (F)''
Data_Type: real
Default_Value: 1.0e12
Limits:
Vector: no
Vector_Bounds:
Null_Allowed: yes
PARAMETER_TABLE:
Parameter_Name: clk_load
Description: ''clock loading capacitance (F)''
Data_Type: real
Default_Value: 1.0e12
Limits:
Vector: no
Vector_Bounds:
Null_Allowed: yes
PARAMETER_TABLE:
Parameter_Name: reset_load
Description: ''reset loading capacitance (F)''
Data_Type: real
Default_Value: 1.0e12
Limits: