This version supports full hierarchical to flat PCB formatted netlists so that 3rd party tools can be used to layout SuperSpice designs. Set PCB data in the component properties dialog e.g. component name (separate from the spice name) and package/footprint name/type. Only Orcad, Protel, Tango, PCLogic and Eagle formatted data is supported at the moment, more might follow.
The PCB netlist name will be the same as the top-level schematic, but with a .net extension.
Naming convention:
If a component is in a subcircuit, say X14, with a reference designator of say, R4, the designator will be expanded to R4:X14. Deeper levels would be e.g. R4:X14:X34:X43. i.e. its position in the stack is given by an appended name by X14:X34:X43. Net names follow the same convention, but with higher level names been passed down directly to maintain connectivity.
Note that:
X4:X14:X34:X43:Pin1[I] means the current in Pin1 of X4, in the descended schematics X14:X34:X43. That is, it is the same as for normal spice devices, or the first X designator is the component within the hierarchy.