Device Current Probing And Saving
Hierarchical Schematic Currents
Currents can be saved and probed in hierarchical schematic subcircuits. This is achieved by setting the SuperSpice program options (blue "PO" button) to "Flat Netlist" (this is the default). In this mode all schematic subcircuits are processed to form one large non hierarchical netlist. In fact, this is the form that most PCB layout software usually requires. The downside on this is that the flat netlist mode takes longer to netlist.
The history to this, is that the original Berkeley code did not include subcircuit current saves directly. The workaround is to add a zero voltage dc source in the required branch, as this current is saved. For most .subckts, e.g. op-amps, the additional voltage sources will not significantly increases the simulation time.
.subckts
Probing of currents into the pins of Spice subckts is achieved by SuperSpice automatically adding in extra zero voltage sources in series to the subckt connection pins. These extra spice lines will be saved in the loaded spice model files. This can be globally disabled in the SuperSpice options dialog. To disable this feature on an individual basis add at least one "!" text character to at least one of the subckt pin lists, and change all reference to the original name to the new name. This will cause SuperSpice to ignore adding pins for that particular subckt. For xspice digial "a" devices in .subckts this feature must be disabled as digital nodes cannot be directly connect to an analog voltage source. For digital connections, the recommended method is to add '#' or '$" to the first letter of digital model names, # being used for inputs, $ being used for outputs. This notation is required to achieve functionality of the auto ADC insert between digital and analog nodes.
e.g. for analogue devices change:
.subckt a_model_name in out vdd vss
....
r1 in out 1k
.ends
to:
.subckt a_model_name in !pin_out vdd vss...
...
r1 in !pin_ out 1k
.ends
or for digital devices change:
.subckt a_model_name &in $out
a1 &in $out inv1
.model inv1 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9)
.ends
AC Current Probing
AC probing of currents is supported for the following devices:
1 Resisters
2 Capacitors
3 Inductors
4 Voltage sources
Specially, AC probing of transistor currents is not supported. The workaround is to probe the current in a series voltage source.
Transient and DC Current Probing
Most devices support Transient and DC current probing. Some exceptions are:
1 Transmission lines
Device Power
Device power waveforms can also be viewed with an alt-click on the spice device itself, or by dragging a test point so that its pin touches the device. This feature requires that saving of currents prior to the simulation are enabled (default mode).
BSim3v3 Models and BSim4v8
The original spice code did not produce output for source, gate, and bulk/substrate currents. The code has been modified so that data is obtained at all pins, and now fully supports DC and Transient current probing and saving.
Notes
For schematic current probing of BSim3v3 models to work correctly, the 4 terminal mosfet should be used, as the bulk diode current is not included in the source terminal probed current. To view bulk currents, the waveform signal list should be used instead.
Bsim1 and Bsim2 do not support this feature, so current saves for these devices are required to be disabled to avoid a simulation load error. This is generally of zero consequence as all modern i.c. design work is de facto done with at Bsim3v3. models.
Inductor Blemish
For worst case sweeps and single parameter sweeps, inductors use a virtual subcircuit, so the current in the inductor in these modes is given by an extra subcircuit designation. Probing with the test points does not support this mode inductor current yet. This is fixable, and at some point, due to some legacy code…
The workaround is to use a rerun file for sweeps. This method treats inductors as inductors.